The invention relates to an analog-to-digital converter.
An analog-to-digital converter (ADC) is an electronic circuit or an electronic chip which converts an analog signal into a digital equivalent. An ADC converts a continuous-value voltage value into a binary number which indicates how often a particular voltage range is included within the voltage value.
Analog-to-digital converters (ADCs) are used at interfaces between analog signals and digital data processing. Fundamental service features of an ADC are the achievable resolution of the converter (measured in bits) and the conversion speed (measured in samples per second: Sa/s). Particularly in the field of communications engineering, there is a need for very fast converters, that is, converters with high conversion rates (for example, >1 GSa/s). The resolution of known converters is normally between 5 bits and 8 bits, and the circuit architecture is based on a flash converter architecture.
FIG. 1 illustrates an analog-to-digital converter 100 which is known from the prior art.
The analog-to-digital converter 100 has a multiplicity of comparators 101 that each have a first input 102, a second input 103 and an output 104. Provided at the first input 102 of each comparator is a signal 108 Vin for digitization in the form of an electrical voltage signal. Connected between a respective second input 103 on a comparator 101 and a positive reference potential 106 Vref+ or a negative reference potential Vref− are a number of nonreactive resistors 105 which are characteristic of each of the comparators. By way of example, a single resistor 105 is connected between the second input 103 of the top comparator 101 in FIG. 1 and the positive reference potential 106, two nonreactive resistors 105 are connected between the second input 103 of the second-from-top comparator 101 in FIG. 1 and the positive reference potential 106 Vref+, etc. The voltage drop across the nonreactive resistors 105 connected between the reference potential 106, 107 and the second input 103 of a respective comparator 101 is used to reduce the potential applied to the second input 103 in FIG. 1 from the top to the bottom in stages, so that a comparative result at the outputs of the comparators 101 supplies a sequence of output values with the logic value “1” and then a sequence of output values with the logic value “0”. This digitized output signal is called a thermometer code, where the number of comparator outputs 104 providing a logic value “1” represents a digitized measure of the value of the signal 108 for digitization.
In the case of the circuit illustrated in FIG. 1 for an analog-to-digital converter 100 based on the prior art, the n comparators 101 compare the input voltage Vin 108 with reference voltages Vref,i which are generated using the resistor network comprising resistors 105. The resistor network is normally in the form of a linear voltage divider which is used to apply a reference voltage Vref+ or Vref−. By using the same resistors 105, the reference voltage Vref=Vref+−Vref− is distributed evenly over the comparators.
Known circuit designs for analog-to-digital converters are based on the “flash” process. In this context, the input voltage Vin 108 for digitization is simultaneously applied to the first inputs 102 of the comparators 101. To achieve a resolution of n bits, 2n−1 comparators 101 are required. The second input 103 of the comparators 101 has respective different subvoltages applied to it that are produced using an integrated reference resistor network comprising the resistors 105. The accuracy or the resolution of the analog-to-digital converter 100 is determined essentially by the accuracy of the reference resistor network and by the offset in the comparators 101. These factors are determined by statistical variations in component parameters, which decrease as the surface area of the components increases.
The conversion speed of an A/D converter 100 is determined primarily by the architecture and by the speed of the comparators 101. Often, a sample-and-hold circuit is connected upstream of the actual converter block, said sample-and-hold circuit storing and holding the input voltage at a particular time in analog form and making it available to the converter block. This also limits the conversion speed and/or the resolution of the converter.
The analog-to-digital converter based on the prior art has a conversion speed which is in need of improvement.
Depending on the model, a comparator has a defined voltage window within which it works in optimum fashion, that is, it provides the comparison result for its two analog input voltages in a sufficiently short time and with sufficient accuracy at the output 104 in digital form. The signal propagation time in a comparator 101 is always dependent on the input voltage for the comparator 101, however. There is an optimum input voltage at which the comparison result is available in comparatively short time. If the input voltage approaches the limits of the voltage window, the propagation time in a comparator increases and the conversion speed is reduced.
In the case of the analog-to-digital converter 100 based on the prior art, each of the comparators 101 operates at a different input voltage. The comparators 101 therefore need to be designed for a wide input voltage range.
Hence, in the case of the described flash architecture based on the prior art, the principle means that a different input voltage is applied to each comparator, which means that each comparator has a different signal propagation time.
To process differential signals in an analog-to-digital converter, the prior art involves the two mutually antiphase input signals for respective independent comparators being converted into a digital signal and then digitally subtracted. In rare cases, complex comparators having four inputs are even used.
U.S. Pat. No. 6,114,982 discloses an analog-to-digital converter having a first resistor ladder between a first reference voltage and a second reference voltage and also having a second resistor ladder whose two end sections are coupled to an analog signal source.
GB 2,187,054 A discloses an analog-to-digital converter having a plurality of amplifiers whose inputs are supplied with an analog signal via a resistor chain.
JP-07254857 A discloses an analog-to-digital converter in which the influence of an offset needs to be reduced and A/D conversion needs to take place sufficiently quickly and accurately.
U.S. Pat. No. 6,437,724 B1 discloses an analog-to-digital converter having two networks of resistor elements to which analog signals are applied and which are coupled to inputs on comparators.
EP 0 729 233 A1 discloses an analog-to-digital converter which can be used to compensate for a comparator offset.